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| IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet innovASIC FEATURES * * * * * * * * * * * * * * * * Form, Fit, and Function Compatible with the Intel(R) 8044/8344 Packaging options available: 40 Pin Plastic Dual In-Line Package (PDIP), 44 Pin Plastic Leaded Chip Carrier (PLCC) 8-Bit Control Unit 8-Bit Arithmetic-Logic Unit with 16-Bit multiplication and division 12 MHz clock Four 8-Bit Input / Output ports Two 16-Bit Timer/Counters Serial Interface Unit with SDLC/HDLC compatibility 2.4 Mbps maximum serial data rate Two Level Priority Interrupt System 5 Interrupt Sources Internal Clock prescaler and Phase generator 192 Bytes of Read/Write Data Memory Space 64kB External Program Memory Space 64kB External Data Memory Space 4kB Internal ROM (IA8044 only) IA8044/IA8344 Variants IA8044 IA8344 4kB internal ROM with R0117 version 2.3 firmware, 192 byte internal RAM, 64kB external program and data space. 192 byte internal RAM, 64kB external program and data space. The IA8044/IA8344 is a "plug-and-play" drop-in replacement for the original IC. InnovASIC produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA8044/IA8344 including functional and I/O descriptions, electrical characteristics, and applicable timing. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 1 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Package Pinout P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 (RTS) P1.6 (CTS) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (SCLK/T1) P3.5 VCC P1.2 P1.1 P1.0 P0.0 P1.4 P1.3 P0.1 P0.2 (41) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) 40 Pin DIP (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (24) (23) (22) (21) P0.0 (AD0) P0.1 (AD1) (44) (43) (42) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) (40) (6) (5) (4) (3) (2) (1) P0.2 (AD2) P1.5 P1.6 P1.7 RST/VPD P3.0 N.C. P3.1 P3.2 P3.3 P3.4 P3.5 N.C. P0.3 (1) IA8X44 (40) VCC (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (39) (38) P0.4 P0.5 P0.6 P0.7 EA N.C. ALE PSEN P2.7 P2.6 P2.5 IA8X44 44 Pin LCC (37) (36) (35) (34) (33) (32) (31) (30) (29) (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 VSS VSS N.C. P2.0 P2.3 XTAL2 XTAL1 P3.6 P3.7 P2.1 P2.1 (A9) P2.0 (A8) DESCRIPTION The IA8044/IA8344 is a form, fit and function compatible part to the Intel(R) 8X44 SDLC communications controller. The IA8044/IA8344 is a Fast Single-Chip 8-Bit Microcontroller with an integrated SDLC/HDLC serial interface controller. The IA8044/IA8344 is a fully functional 8-Bit Embedded Controller that executes all ASM51 instructions and has the same instruction set as the Intel 80C51. The IA8044/IA8344 can access the instructions from two types of program memory, serves software and hardware interrupts, provides an interface for serial communications and a timer system. The IA8044/IA8344 is fully compatible with the Intel(R) 8X44 series. The functional block diagram is shown below. Copyright (c) 2003 ENG210010112-00 P2.2 P2.4 innovASIC The End of ObsolescenceTM Page 2 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Functional Block Diagram I/O for Memory, SIU, DMA, Interrupts, Timers Port 0 ADDR/DATA/IO Port 2 ADDR/DATA/IO Port 1 SPCL FUNC/IO Port 3 SPCL FUNC/IO Memory Control XTAL Reset Clock Gen. & Timing 192x8Dual Port RAM C8051 CPU Control Address/Data Interrupts SIU Timers Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 3 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet I/O Characteristics The table below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. The table below provides the I/O description of the IA8044 and the IA8344. Name RST ALE PSEN EA P0.7 - P0.0 P1.7 - P1.0 P2.7 - P2.0 P3.7 - P3.0 Type I O O I I/O I/O I/O I/O Description Reset. This pin when held high for two machine cycles while the oscillator is running will cause the chip to reset. Address Latch Enable. Used to latch the address on the falling edge for external memory accesses. Program Store Enable. When low acts as an output enable for external program memory. External Access. When held low EA will cause the IA8044/IA8344 to fetch instructions from external memory. Port 0. 8 bit I/O port and low order multiplexed address/data byte for external accesses. Port 1. 8-bit I/O port. Two bits have alternate functions, P1.6 (RTS) and P1.7 (CTS). Port 2. 8-bit I/O port. It also functions as the high order address byte during external accesses. Port 3. 8-bit I/O port. Port 3 bits also have alternate functions as described below. P3.0 - RXD. Receive data input for SIU or direction control for P3.1 dependent upon datalink configuration. P3.1 - TXD. Transmit data output for SIU or data input/output dependent upon datalink configuration. Also enables diagnostic mode when cleared. P3.2 - INT0. Interrupt 0 input or gate control input for counter 0. P3.3 - INT1. Interrupt 1 input or gate control input for counter 1. P3.4 - T0. Input to counter 0. P3.5 - SCLK/T1. SCLK input to SIU or input to counter 1. P3.6 - WR. External memory write signal. P3.7 - RD. External memory read signal. Crystal Input 1. Connect to VSS when external clock is used on XTAL2. May be connected to a crystal (with XTAL2), or may be driven directly with a clock source (XTAL2 not connected). Crystal Input 2. May be connected to a crystal (with XTAL1), or may be driven directly with an inverted clock source (XTAL1 tied to ground). Ground. +5V power. XTAL1 XTAL2 VSS VCC I O P P Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 4 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Memory Organization Program Memory Program Memory includes interrupt and Reset vectors. The interrupt vectors are spaced at 8byte intervals, starting from 0003H for External Interrupt 0. Reset Vectors Location 0003H 000BH 0013H 001BH 0023H Service External Interrupt 0 Timer 0 overflow External Interrupt 1 Timer 1 overflow SIU Interrupt These locations may be used for program code, if the corresponding interrupts are not used (disabled). The Program Memory space is 64K, from 0000H to FFFFH. The lowest 4K of program code (0000H to 0FFFH) can be fetched from external or internal Program Memory. This selection is made by strapping pin `EA' (External Address) to GND or VCC. If during reset, `EA' is held low, all the program code is fetched from external memory. If, during reset, `EA' is held high, the lowest 4K of program code (0000H to 0FFFH) is fetched from internal memory (ROM). Program memory addresses above 4K (0FFFH) will cause the program code to be fetched from external memory regardless of the setting of `EA'. Data Memory External Data Memory The IA8044/IA8344 Microcontroller core incorporates the Harvard architecture, with separate code and data spaces. The code from external memory is fetched by `psen' strobe, while data is read from RAM by bit 7 of P3 (read strobe) and written to RAM by bit 6 of P3 (write strobe). The External Data Memory space is active only by addressing through use of the MOVX instruction and the 16-bit Data Pointer Register (DPTR). A smaller subset of external data memory (8 bit addressing) may be accessed by using the MOVX instruction with register indexed addressing. Internal Data Memory The Internal Data Memory address is always 1 byte wide. The memory space is 192 bytes large (00H to BFH), and can be accessed by either direct or indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Internal memory that overlaps the SFR address space is only accessible by indirect addressing. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 5 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Internal Memory FFh BFh Special Function Registers Addressable BITS in SFRs (128 BITS) Indirect Addressing RAM 80h 7Fh 80h Direct Addressing 30h 2Fh Bit Addressable Memory 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h Internal Data Ram 8044 Internal Data Memory Addresses 00h to FFh Register Bank 3 Register Bank 2 Register Bank 1 Register Bank 0 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 6 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Bit Addressable Memory Both the internal RAM and the Special Function Registers have locations that are bit addressable in addition to the byte addressable locations. SFR Bit Addressable Locations Byte Address F0h E0h D8h D0h C8h B8h B0h A8h A0h 90h 88h 80h bit 7 F7h E7h DFh D7h CFh B7h AFh A7h 97h 8Fh 87h bit 6 F6h E6h DEh D6h CEh B6h A6h 96h 8Eh 86h bit 5 F5h E5h DDh D5h CDh B5h A5h 95h 8Dh 85h bit 4 F4h E4h DCh D4h CCh BCh B4h ACh A4h 94h 8Ch 84h bit 3 F3h E3h DBh D3h CBh BBh B3h ABh A3h 93h 8Bh 83h bit 2 F2h E2h DAh D2h CAh BAh B2h AAh A2h 92h 8Ah 82h bit 1 F1h E1h D9h D1h C9h B9h B1h A9h A1h 91h 89h 81h bit 0 F0h E0h D8h D0h C8h B8h B0h A8h A0h 90h 88h 80h Register B ACC NSNR PSW STS IP P3 IE P2 P1 TCON P0 Internal RAM Bit Addressable Locations Byte Address 30h-BFh 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 18h-1Fh 10h-17h 08h-0Fh 00h-07h bit 7 7Fh 77h 6Fh 67h 5Fh 57h 4Fh 47h 3Fh 37h 2Fh 27h 1Fh 17h 0Fh 07h bit 6 7Eh 76h 6Eh 66h 5Eh 56h 4Eh 46h 3Eh 36h 2Eh 26h 1Eh 16h 0Eh 06h bit 5 bit 4 bit 3 bit 2 Upper Internal Ram locations 7Dh 7Ch 7Bh 7Ah 75h 74h 73h 72h 6Dh 6Ch 6Bh 6Ah 65h 64h 63h 62h 5Dh 5Ch 5Bh 5Ah 55h 54h 53h 52h 4Dh 4Ch 4Bh 4Ah 45h 44h 43h 42h 3Dh 3Ch 3Bh 3Ah 35h 34h 33h 32h 2Dh 2Ch 2Bh 2Ah 25h 24h 23h 22h 1Dh 1Ch 1Bh 1Ah 15h 14h 13h 12h 0Dh 0Ch 0Bh 0Ah 05h 04h 03h 02h Register Bank 3 Register Bank 2 Register Bank 1 Register Bank 0 bit 1 79h 71h 69h 61h 59h 51h 49h 41h 39h 31h 29h 21h 19h 11h 09h 01h bit 0 78h 70h 68h 60h 58h 50h 48h 40h 38h 30h 28h 20h 18h 10h 08h 00h Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 7 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Instruction Set The 8X44 architecture and instruction set are identical to the 8051's. The following tables give a survey of the instruction set of the IA8044/IA8344 Microcontroller core. Arithmetic Operations Mnemonic ADD A,Rn ADD A, direct ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,direct ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,direct SUBB A,@Ri SUBB A,#data INC A INC Rn INC direct INC @ Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL A,B DIV A,B DA A Description Add register to accumulator Add direct byte to accumulator Add indirect RAM to accumulator Add immediate data to accumulator Add register to accumulator with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment accumulator Increment register Increment direct byte Increment indirect RAM Decrement accumulator Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A and B Divide A by B Decimal adjust accumulator Byte Cycle 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 8 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Logic Operations Mnemonic ANL A,Rn ANL A,direct ANL A,@Ri ANL A,#data ANL direct,A ANL direct,#data ORL A,Rn ORL A,direct ORL A,@Ri ORL A,#data ORL direct,A ORL direct,#data XRL A,Rn XRL A,direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data CLR A CPL A RL A RLC A RR A RRC A SWAP A Description AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulator AND immediate data to accumulator AND accumulator to direct byte AND immediate data to direct byte OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator OR accumulator to direct byte OR immediate data to direct byte Exclusive OR register to accumulator Exclusive OR direct byte to accumulator Exclusive OR indirect RAM to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to direct byte Exclusive OR immediate data to direct byte Clear accumulator Complement accumulator Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Swap nibbles within the accumulator Data Sheet Byte Cycle 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 9 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Data Transfer Mnemonic Description Byte Cycle 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 MOV A,Rn Move register to accumulator MOV A,direct Move direct byte to accumulator MOV A,@Ri Move indirect RAM to accumulator MOV A,#data Move immediate data to accumulator MOV Rn,A Move accumulator to register MOV Rn,direct Move direct byte to register MOV Rn,#data Move immediate data to register MOV direct,A Move accumulator to direct byte MOV direct,Rn Move register to direct byte MOV direct,direct Move direct byte to direct byte MOV direct,@Ri Move indirect RAM to direct byte MOV direct,#data Move immediate data to direct byte MOV @Ri,A Move accumulator to indirect RAM MOV @Ri,direct Move direct byte to indirect RAM MOV @ Ri, #data Move immediate data to indirect RAM MOV DPTR, #data16 Load data pointer with a 16-bit constant MOVC A,@A + DPTR Move code byte relative to DPTR to accumulator MOVC A,@A + PC Move code byte relative to PC to accumulator MOVX A,@Ri Move external RAM (8-bit addr.) to A MOVX A,@DPTR Move external RAM (16-bit addr.) to A MOVX @Ri,A Move A to external RAM (8-bit addr.) MOVX @DPTR,A Move A to external RAM (16-bit addr.) PUSH direct Push direct byte onto stack POP direct Pop direct byte from stack XCH A,Rn Exchange register with accumulator XCH A,direct Exchange direct byte with accumulator XCH A,@Ri Exchange indirect RAM with accumulator XCHD X,@ Ri Exchange low-order nibble indir. RAM with A Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 10 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Boolean Manipulation Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,bit ORL C,bit ORL C,bit MOV C,bit MOV bit,C Description Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry OR direct bit to carry flag OR complement of direct bit to carry Move direct bit to carry flag Move carry flag to direct bit Byte Cycle 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 Program Branches Mnemonic ACALL addr11 LCALL addr16 RET Return RETI Return AJMP addr11 LJMP addr16 SJMP rel JMP @A + DPTR JZ rel JNZ rel JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel CJNE A,direct,rel CJNE A,#data,rel CJNE Rn,#data rel CJNE @Ri,#data,rel DJNZ Rn,rel DJNZ direct,rel NOP Copyright (c) 2003 Description Absolute subroutine call Long subroutine call from subroutine from interrupt Absolute jump Long jump Short jump (relative addr.) Jump indirect relative to the DPTR Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immed. to reg. and jump if not equal Compare immed. to ind. and jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero No operation ENG210010112-00 Byte Cycle 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 www.innovasic.com Customer Support: 1-888-824-4184 innovASIC The End of ObsolescenceTM Page 11 of 49 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Special Function Registers The IA8044/IA8344 contains the following special function registers: Symbol ACC B PSW SP DPH DPL P0 P1 P2 P3 IP IE TMOD TCON TH0 TL0 TH1 TL1 SMD STS NSNR STAD TBS TBL TCB RBS RBL RFL RCB DMA CNT FIFO SIUST Register Description Accumulator B register Program Status Word Stack Pointer Data Pointer High Byte Data Pointer Low Byte Port 0 Port 1 Port 2 Port 3 Interrupt Priority Interrupt Enable Timer/Counter Mode Timer/Counter Control Timer/Counter 0 high byte Timer/Counter 0 low byte Timer/Counter 1 high byte Timer/Counter 1 low byte Serial Mode SIU Status and Command SIU Send/Receive Count SIU Station Address Transmit Buffer Start Address Transmit Buffer Length Transmit Control Byte Receive Buffer Start Address Receive Buffer Length Receive Field Length Receive Control Byte DMA Count FIFO contents (3 bytes) SIU State Counter Byte Address(Hex) E0h F0h D0h 81h 82h 83h 80h 90h A0h B0h B8h A8h 89h 88h 8Ch 8Ah 8Dh 8Bh C9h C8h D8h CEh DCh DBh DAh CCh CBh CDh CAh CFh DF,DE,DDh D9h Bit Addresses (Hex) (MSB - LSB) E7h - E0h F7h - F0h D7h - D0h 87h - 80h 97h - 90h A7h - A0h B7h - B0h BCh - B8h AFh,ACh - A8h 8Fh - 88h CFh - C8h DFh - D8h - Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 12 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Ports Data Sheet Ports P0, P1, P2 and P3 are Special Function Registers. The contents of the SFR can be observed on corresponding pins on the chip. Writing a `1' to any of the ports causes the corresponding pin to be at high level (VCC), and writing a `0' causes the corresponding pin to be held at low level (GND). All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0 to P3), an output driver, and an input buffer, so the CPU can output or read data through any of these ports if they are not used for alternate purposes. Ports P0, P1, P2 and P3 can perform some alternate functions. Ports P0 and P2 are used to access external memory. In this case, port `p0' outputs the multiplexed lower 8 bits of address with `ale' strobe high and then reads/writes 8 bits of data. Port P2 outputs the higher 8 bits of address. Keeping `ea' pin low (tied to GND) activates this alternate function for ports P0 and P2. Port P3 and P1 can perform some alternate functions. The pins of Port P3 are multifunctional. They can perform additional functions as described below. Pin P3.0 Symbol RxD, I/O Function In point-to-point or multipoint configurations (SMD.3 = 0) this pin is I/O and signals the direction of data flow on DATA (P3.1). In loop mode (SMD.3 = 1) and diagnostic mode this pin is RxD, Receive Data input. P3.1 TxD, DATA In point to point or multipoint configurations (SMD.3 = 0) this pin is DATA and is the transmit/receive data pin. In loop mode (SMD.3 = 1) this pin is the transmit data, TxD, pin. Writing a `0' to this port buffer bit enables the diagnostic mode. INT0 INT1 T0 External interrupt 0 input. Also gate control input for counter 0. External interrupt 1 input. Also gate control input for counter 1. Timer/Counter 0 external input. Setting the appropriate bits in the Special Function Registers TCON and TMOD activates this function. Timer/Counter 1 external input. Setting the appropriate bits in the Special Function Registers TCON and TMOD activates this function. . Can also function as the external clock source for the SIU. External Data Memory write strobe, active LOW. This function is activated by a CPU write access to External Data Memory (i.e. MOVX @DPTR, A). P3.2 P3.3 P3.4 P3.5 T1, SCLK P3.6 WR Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 13 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet P3.7 RD External Data Memory read strobe, active LOW. This function is activated by a CPU read access from External Data Memory (i.e. MOVX A, @DPTR). Request To Send output, active low. Clear To Send input, active low. P1.6 P1.7 RTS CTS Port Registers Port 0 (P0): General purpose, 8 bit, I/O port and multiplexed low order address and data bus with open-drain output buffers. P0 Bit: 7 P0.7 6 P0.6 5 P0.5 4 P0.4 P0.3 3 P0.2 2 P0.1 1 P0.0 0 Port 1 (P1): General purpose, 8 bit, I/O port with pullups and auxiliary functions. P1 Bit: 7 RTS/P1.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 6 CTS/P1.6 RTS CTS 5 P1.5 4 P1.4 3 P1.3 2 P1.2 1 P1.1 0 P1.0 Request To Send output. Clear To Send input. Port 2 (P2): General purpose, 8 bit, I/O port with pullups and high order address bus. P2 Bit: 7 P2.7 6 P2.6 5 P2.5 4 P2.4 3 P2.3 2 P2.2 1 P2.1 0 P2.0 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 14 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Port 3 (P3): Data Sheet General purpose, 8-bit I/O port with pullups and auxiliary functions. Bits on this port also functions as the SIU data transmit/receive I/O, external interrupt inputs, timer inputs and the read and write strobes for external memory accesses. P3 Bit: 7 RD P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 6 WR RxD TxD INT0 INT1 T0 T1 WR RD T1 5 T0 4 3 INT1 2 INT0 1 TxD RxD 0 Serial input pin. Serial output pin. External interrupt 0. External interrupt 1. Timer/Counter 0 external input. Timer/Counter 1 external input. External Data Memory write strobe, active LOW. External Data Memory read strobe, active LOW. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 15 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Timers/Counters Timers 0 and 1 The IA8X44 has two 16-bit timer/counter registers: Timer 0 and Timer 1. Both can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, which means that it counts up after every 12 oscillator periods. In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0 or T1. Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle (12 clock periods). Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to select the appropriate mode. Mode 0 In mode 0 the timers operate as an 8-bit timer (TH0/1) with a divide by 32 bit prescalar (TL0/1). Mode 0 uses all 8 bits of TH0/1 and the lower 5 bits of TL0/1. The upper 3 bits of TL0/1 are unknowns. Setting TR0/1 does not reset the registers TH0/1 and TL0/1. As the timer rolls over from all 1's to all 0's it will set the interrupt flag TF0/1. Mode 1 Mode 1 is the same as mode 0 except that all 8 bits of TL0/1 are used instead of just the lower 5 bits. Mode 2 Mode 2 configures TL0/1 as an 8-bit counter with automatic reload from the contents of TH0/1. Overflow of TL0/1 causes the interrupt TF0/1 to be set and the reload to occur. The contents of TH0/1 are not affected by the reload. Mode 3 Mode 3 creates two separate 8 bit counters from TL0 and TH0. TL0 uses the timer 0 mode bits from TMOD, TMOD .0 through TMOD.3. TH0 is a timer only (not a counter) and uses timer 1's control bits, TR1 and TF1 for operation. Timer 1 can still be used if an interrupt is not required by switching it in and out of its own mode 3. With TMOD.4 and TMOD.5 both high timer 1 will stop and hold its count. Timer Mode (TMOD): The Timer Mode register contains bits that select the mode that the timers are to be operated in. The lower nibble controls timer 0 and the upper nibble controls timer 1. TMOD Bit: 7 GATE TMOD.0 Copyright (c) 2003 6 C/T M1 M0 5 M0 4 3 GATE 2 C/T M1 1 M0 0 Timer 0 mode selector bit. ENG210010112-00 www.innovasic.com Customer Support: 1-888-824-4184 innovASIC The End of ObsolescenceTM Page 16 of 49 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER TMOD.1 TMOD.2 TMOD.3 M1 C/T GATE Data Sheet TMOD.4 TMOD.5 TMOD.6 TMOD.7 M0 M1 C/T GATE Timer 0 mode selector bit. C/T Selects Timer0 or Counter0 operation. When set to 1, the Counter operation is performed, when cleared to 0, the register will function as a Timer. If set, enables external gate control for counter/timer0 (pin INT0/ for Counter 0). When INT0/ is high, and TR0 bit is set (see TCON register), the counter is incremented every falling edge on T0 input pin. Timer 1 mode selector bit. Timer 1 mode selector bit. C/T Selects Timer1 or Counter1 operation. When set to 1, the Counter operation is performed, when cleared to 0, the register will function as a Timer. If set, enables external gate control for counter/timer1 (pin INT1/ for Counter 1). When INT1/ is high, and TR1 bit is set (see TCON register), the counter is incremented every falling edge on T1 input pin.. Timer Mode Select Bits M1 M0 Operating Mode 0 0 0 13 bit timer 0 1 1 16 bit timer/counter 1 0 2 8 bit auto-reload timer/counter 1 1 3 Timer0 - TL0 is a standard 8-bit timer/counter controlled by timer 0 control bits. TH0 is an 8-bit timer function only, controlled by timer 1 control bits. 1 1 3 Timer/counter1 stopped and holds its count. Can be used to start/stop timer 1 when timer 0 is in mode 3. Timer Control (TCON): The Timer Control register provides control bits that start and stop the counters. It also contains bits to select the type of external interrupt desired, edge or level. Additionally TCON contains status bits showing when a timer overflows and when an interrupt edge has been detected. TCON Bit: 7 TF1 TCON.0 TCON.1 TCON.2 Copyright (c) 2003 6 TR1 TF0 IT0 IE0 IT1 5 TR0 4 IE1 3 IT1 2 IE0 1 IT0 0 Interrupt 0 type control bit. Selects falling edge or low level on input pin to cause interrupt. Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT1/ is observed. Cleared when interrupt is processed. Interrupt 1 type control bit. Selects falling edge or low level on input pin to cause interrupt. ENG210010112-00 www.innovasic.com Customer Support: 1-888-824-4184 innovASIC The End of ObsolescenceTM Page 17 of 49 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER TCON.3 TCON.4 TCON.5 TCON.6 TCON.7 IE1 TR0 TF0 TR1 TF1 Data Sheet Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1/ is observed Cleared when interrupt is processed. Timer 0 Run control bit. If cleared, Timer 0 stops. Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag should be cleared by software. Timer 1 Run control bit. If cleared, Timer 1 stops. In mode 3 this bit controls TH0. Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag should be cleared by software.. In mode 3 this bit is controlled by TH0. Timer 0 High byte (TH0): High order byte of timer/counter0. TH0 Bit: 7 TH0.7 6 TH0.6 5 TH0.5 4 TH0.4 3 TH0.3 2 TH0.2 1 TH0.1 0 TH0.0 Timer 0 Low byte (TL0): Low order byte of timer/counter0. TL0 Bit: 7 TL0.7 6 TL0.6 5 TL0.5 4 TL0.4 3 TL0.3 2 TL0.2 1 TL0.1 0 TL0.0 Timer 1 High byte (TH1): High order byte of timer/counter1. TH1 Bit: 7 TH1.7 6 TH1.6 5 TH1.5 4 TH1.4 3 TH1.3 2 TH1.2 1 TH1.1 0 TH1.0 Timer 1 Low byte (TL1): Low order byte of timer/counter1. TL1 Bit: 7 TL1.7 6 TL1.6 5 TL1.5 4 TL1.4 3 TL1.3 2 TL1.2 1 TL1.1 0 TL1.0 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 18 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Timers/Counters Configuration Timer 0 Mode 0 OSC / 12 C/ T = 0 TLO (5 BITS ) P3.4/T0 =1 Gate C/ T = 1 Control TH0 (8 BITS) TF0 Data Sheet Interrupt TR0 & 1 P3.2/INT0 Timer 0 Mode 1 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 19 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Timer 0 Mode 2 OSC / 12 C/ T = 0 TLO (8 BITS ) P3.4/T0 =1 Gate C/ T = 1 Control Reload TF0 Interrupt TR0 & 1 P3.2/INT0 TH0 (8 BITS) Timer 0 Mode 3 OSC / 12 C/ T = 0 1/12 fOSC TLO (8 BITS ) P3.4/T0 =1 Gate C/ T = 1 Control TF0 Interrupt TR0 & 1 P3.2/INT0 1/12 fOSC TH0 (8 BITS) TF1 Interrupt TR1 Control Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 20 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Reset Data Sheet A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU responds by generating an internal reset, which is executed during the second cycle in which RST is high. The internal reset sequence affects all SFRs as shown below. The internal reset sequence does not affect the contents of internal RAM. Reset Values Register PC ACC B PSW SP DPTR P0 - P3 IP IE TMOD TCON TH0 TL0 TH1 TL1 SMD STS NSNR STAD TBS TBL TCB RBS RBL RFL RCB DMA CNT FIFO1 FIFO2 FIFO3 SIUST Reset value 0000H 00000000B 00000000B 00000000B 00000111B 0000H 11111111B XXX00000B 0XX00000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 00000001B Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 21 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER General CPU Registers Accumulator (ACC): Data Sheet ACC is the Accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. ACC Bit: 7 ACC.7 6 ACC.6 5 ACC.5 4 ACC.4 3 ACC.3 2 ACC.2 1 ACC.1 0 ACC.0 B register (B): The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data. B Bit: 7 B.7 6 B.6 B.5 5 B.4 4 B.3 3 B.2 2 B.1 1 B.0 0 Program Status Word (PSW): Contains CPU status flags, register select bits and user flags. PSW Bit: 7 CY PSW.0 PSW.1 PSW.2 PSW.3 PSW.4 PSW.5 PSW.6 PSW.7 6 AC P OV RS0 RS1 F0 AC CY F0 5 RS1 4 RS0 3 OV 2 1 P 0 Parity flag, affected by hardware to indicate odd / even number of "one" bits in the Accumulator, i.e. even parity. User defined flag. Overflow flag. Register bank select control bit 0, used to select working register bank. Register bank select control bit 1, used to select working register bank. General purpose Flag 0 available for user. Auxiliary Carry flag for carry out of or into bit 3. Carry flag for carry out of or into bit 7. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 22 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER The state of bits RS1, RS0 selects the working registers bank as follows: RS1/0 00 01 10 11 Bank selected location Bank 0 (00H - 07H) Bank 1 (08H - 0FH) Bank 2 (10H - 17H) Bank 3 (18H - 1FH) Data Sheet Stack Pointer (SP): The Stack Pointer is a 1-byte register initialized to 07H after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 08H. The stack pointer points to a location in internal RAM. SP Bit: 7 SP.7 6 SP.6 SP.5 5 SP.4 4 SP.3 3 SP.2 2 SP.1 1 SP.0 0 Data Pointer (DPTR): The Data Pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as 2 byte register (MOV DPTR,#data16) or as two registers (ea. MOV DPL,#data8). It is generally used to access external code or data space (ea. MOVC A,@A+DPTR or MOV A,@DPTR respectively). DPH Bit: 7 DPH.7 DPL Bit: 7 DPL.7 6 DPH.6 5 DPH.5 4 DPH.4 3 DPH.3 2 DPH.2 1 DPH.1 0 DPH.0 6 DPL.6 5 DPL.5 4 DPL.4 3 DPL.3 2 DPL.2 1 DPL.1 0 DPL.0 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 23 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Interrupts Data Sheet The IA8044/IA8344 provides 5 interrupt sources. There are 2 external interrupts accessible through pins INT0 and INT1, edge or level sensitive (falling edge or low level). There are, also, internal interrupts associated with Timer 0 and Timer 1, and an internal interrupt from the SIU. External Interrupts The choice between external interrupt level or transition activity is made by setting IT1 and IT0 bits in the Special Function Register TCON. When the interrupt event happens, a corresponding Interrupt Control Bit is set (IT0 or IT1). This control bit triggers an interrupt if the appropriate interrupt bit is enabled. When the interrupt service routine is vectored, the corresponding control bit (IT0 or IT1) is cleared provided that the edge triggered mode was selected. If level mode is active, the external requesting source controls flags IT0 or IT1 by the logic level on pins INT0 or INT1 (0 or 1). Timer0 and Timer 1 Interrupts Timer 0 and 1 interrupts are generated by TF0 and TF1 flags, which are set by the rollover of Timer 0 and 1, respectively. When an interrupt is generated, the flag that caused this interrupt is cleared by the hardware, if the CPU accessed the corresponding interrupt service vector. This can be done only if this interrupt is enabled in the IE register. Serial Interface Unit Interrupt The SIU generates an interrupt when a frame is received or transmitted. No interrupts are generated for a received frame with errors. Interrupt Priority Level Structure There are two priority levels in the IA8044/IA8344, and any interrupt can be individually programmed to a high or low priority level. Modifying the appropriate bits in the Special Function Register IP can accomplish this. A low priority interrupt service routine will be interrupted by a high priority interrupt. However, the high priority interrupt can not be interrupted. If two interrupts of the same priority level occur, an internal polling sequence determines which of them will be processed first. This polling sequence is a second priority structure defined as follows: IE0 1 - highest TF0 2 IE1 3 TF1 4 SIU - lowest Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 24 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Interrupt Handling Data Sheet The interrupt flags are sampled during each machine cycle. The samples are polled during the next machine cycle. If an interrupt flag is captured, the interrupt system will generate an LCALL instruction to the appropriate service routine, provided that this is not disabled by the following conditions: 1. An interrupt of the same or higher priority is processed 2. The current machine cycle is not the last cycle of the instruction (the instruction can not be interrupted). 3. The instruction in progress is RETI or any write to IE or IP registers. Note that if an interrupt is disabled and the interrupt flag is cleared before the blocking condition is removed, no interrupt will be generated, since the polling cycle will not sample any active interrupt condition. In other words, the interrupt condition is not remembered. Every polling cycle is new. Interrupt Priority Register (IP): This register sets the interrupt priority to high or low for each interrupt. When the bit is set it selects high priority. Within each level the interrupts are prioritized as follows: External interrupt 0 Timer/counter 0 External interrupt 1 Timer/counter 1 SIU. An interrupt process routine cannot be interrupted by an interrupt of lesser or equal priority. IP Bit: 7 IP.0 IP.1 IP.2 IP.3 IP.4 IP.5 IP.6 IP.7 6 PX0 PT0 PX1 PT1 PS 5 4 PS PT1 3 2 PX1 1 PT0 PX0 0 External Interrupt 0 interrupt priority bit. Timer 0. interrupt priority bit. External interrupt 1. interrupt priority bit. Timer 1 interrupt priority bit. SIU interrupt priority bit. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 25 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Interrupt Enable Register (IE): Data Sheet Contains the global interrupt enable bit and individual interrupt enable bits. Setting a bit enables the corresponding interrupt. IE Bit: 7 EA PCON.0 PCON.1 PCON.2 PCON.3 PCON.4 PCON.5 PCON.6 PCON.7 6 EX0 ET0 EX1 ET1 ES EA 5 4 ES ET1 3 EX1 2 ET0 1 0 EX0 External Interrupt 0 interrupt enable bit. Timer 0. interrupt enable bit. External interrupt 1. interrupt enable bit. Timer 1 interrupt enable bit. SIU interrupt enable bit. Enable All interrupts bit. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 26 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER SIU - Serial Interface Unit Data Sheet The SIU is a serial interface customized to support SDLC/HDLC protocol. As such it supports Zero Bit insertion/deletion, flags automatic access recognition and a 16 bit CRC. The SIU has two modes of operation AUTO and FLEXIBLE. The AUTO mode uses a subset of the SDLC protocol implemented in hardware. This frees the CPU from having to respond to every frame but limits the frame types. In the FLEXIBLE mode every frame is under CPU control and therefore more options are available. The SIU is controlled by and communicates to the CPU by using several special function registers (SFRs). Data transmitted by or received by the SIU is stored in the 192 byte internal RAM in blocks referred to as the transmit and receive buffers. The SIU can support operation in one of three serial data link configurations: 1) half-duplex, point-to-point, 2) half-duplex, multipoint, 3) loop mode. SIU Special Function Registers The CPU controls the SIU and receives status from the SIU via eleven special function registers. The Serial Interface Unit Control Registers are detailed below: Serial Mode Register (SMD): The serial mode register sets the operational mode of the SIU. The CPU can read and write SMD. The SIU can read SMD. To prevent conflicts between CPU and SIU accesses to SMD the CPU should write SMD only when RTS and RBE bits in the STS register are both zero. SMD is normally only accessed during initialization. This register is byte addressable. SMD Bit: 7 6 5 4 3 2 1 0 SCM2 SCM1 SCM0 NRZI LOOP PFS NB NFCS SMD.0 SMD.1 SMD.2 NFCS NB PFS When set selects No FCS field contained in the SDLC frame. Non-buffered mode. No control field contained in SDLC frame. Pre-frame sync mode. When set causes two bytes to be transmitted before the first flag of the frame for DPLL synchronization. If NRZI is set 00H is transmitted otherwise 55H. This ensures that 16 transitions are sent before the opening flag. When set selects loop configuration else point-to-point mode. When set selects NRZI encoding otherwise NRZ. Select clock mode - bit 0. Select clock mode - bit 1. Select clock mode - bit 2. SMD.3 SMD.4 SMD.5 SMD.6 SMD.7 LOOP NRZI SCM0 SCM1 SCM2 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 27 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER SMD Select Clock Mode Bits SCM 210 000 001 010 011 100 101 110 111 Clock Mode Data Rate (Bits/sec)* 0 - 2.4M** Data Sheet Externally clocked Undefined Self clocked, timer overflow 244 - 62.5K Undefined Self clocked, external 16X 0 - 375K Self clocked, external 32X 0 - 187.5K Self clocked, internal fixed 375K Self clocked, internal fixed 187.5K * based on a12 MHz crystal frequency ** 0 - 1M bps in loop configuration Status/Command Register (STS): The Status/Command register provides SIU control from and status to the CPU. The SIU can read the STS and can write certain bits in the STS. The CPU can read and write the STS. Accessing the STS by the CPU via 2 cycle instructions (JBC bit,rel and MOV bit,C) should not be used. STS is bit addressable. STS Bit: 7 TBF STS.0 STS.1 6 RBE RBP AM 5 RTS 4 SI 3 BOV 2 OPB 1 AM 0 RBP STS.2 STS.3 STS.4 STS.5 OPB BOV SI RTS Receive buffer protect. When set prevents writing of data into the receive buffer. Causes RNR response instead of RR in AUTO mode. Auto mode. Dual purpose bit depending upon the setting of bit NB (SMD.1). If NB is cleared, AM selects the AUTO mode when set, Flexible mode when clear. If NB is set, AM selects the addressed mode when set and the non-addressed mode when clear. The SIU can clear AM. Optional poll bit. When set the SIU will AUTO respond to an optional poll (UP with P=0). The SIU can set or clear the OPB. Receive buffer overrun. The SIU can set or clear BOV. SIU interrupt. This bit is set by the SIU and should be cleared by the CPU before returning from the interrupt routine. Request to send. This bit is set when the SIU is ready to transmit or is transmitting. May be written by the SIU in AUTO mode. RTS is only applied to the external pin in non-loop mode. Can be thought of as a Transmit Enable. Note: RTS signal at the pin (P1.6) is the inverted version of this bit. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 28 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER STS.6 RBE Data Sheet STS.7 TBF Receive buffer empty. RBE is set by the CPU when it is ready to receive a frame or has just read the buffer. RBE is cleared by the SIU when a frame has been received. Can be thought of as a Receive Enable. Transmit buffer full. TBF is set by the CPU to indicate that the transmit buffer is ready and TBF is cleared by the SIU. Send/Receive count register (NSNR): The NSNR contains both the transmit and receive sequence numbers in addition to the tally error indications. The CPU can read and write the STS. Accessing the STS by the CPU via 2 cycle instructions (JBC bit,rel and MOV bit,C) should not be used. The SIU can read and write the NSNR. The NS and NR counters are not used in non-AUTO mode. NSNR is bit addressable. NSNR Bit: 7 NS2 NSNR.0 NSNR.1 NSNR.2 NSNR.3 NSNR.4 NSNR.5 NSNR.6 NSNR.7 6 NS1 SER NR0 NR1 NR2 SES NS0 NS1 NS2 5 NS0 4 SES 3 NR2 2 NR1 1 NR0 0 SER Sequence error receive. NS (P) ? NR (S). Receive sequence counter, Bit 0. Receive sequence counter, Bit 1. Receive sequence counter, Bit 2. Sequence error send. NR (P) ? NS (S) and NR (P) ? NS (S) + 1. Send sequence counter, Bit 0. Send sequence counter, Bit 1. Send sequence counter, Bit 2. Station Address register (STAD): The STAD contains the station address (node address) of the chip. The CPU can read or write STAD but should access STAD only when RTS = 0 and RBE = 0. Normally STAD is accessed only during initialization. STAD is byte addressable. STAD Bit: 7 STAD.7 6 STAD.6 5 STAD.5 4 STAD.4 3 STAD.3 2 STAD.2 1 STAD.1 0 STAD.0 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 29 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Transmit Buffer Start Address Register (TBS): Data Sheet The TBS contains the address in internal RAM where the frame (starting with the I-field) to be transmitted is stored. The CPU should access TBS only when the SIU is not transmitting a frame, TBF = 0. TBS is byte addressable. TBS Bit: 7 TBS.7 6 TBS.6 5 TBS.5 4 TBS.4 3 TBS.3 2 TBS.2 1 TBS.1 0 TBS.0 Transmit Buffer Length Register (TBL): The TBL contains the length, in number of bytes, of the I-field to be transmitted. TBL = 0 is valid (no I-field). The CPU should access TBL only when the SIU is not transmitting a frame, TBF = 0. The transmit buffer will not wrap around after address 191 (BFH). A buffer end is automatically generated when address 191 is reached. TBL is byte addressable. TBL Bit: 7 TBL.7 6 TBL.6 5 TBL.5 4 TBL.4 3 TBL.3 2 TBL.2 1 TBL.1 0 TBL.0 Transmit Control Byte Register (TCB): The TCB contains the byte to be placed in the control field of the transmitted frame during nonAUTO mode transmission. The CPU should access TCB only when the SIU is not transmitting a frame, TBF = 0. TCB is byte addressable. TCB Bit: 7 TCB.7 6 TCB.6 5 TCB.5 4 TCB.4 3 TCB.3 2 TCB.2 1 TCB.1 0 TCB.0 Receive Buffer Start Address Register (RBS): The RBS contains the address in internal RAM where the frame (starting with the I-field) being received is to be stored. The CPU should write RBS only when the SIU is not receiving a frame, RBE = 0. RBS is byte addressable. RBS Bit: 7 RBS.7 6 RBS.6 5 RBS.5 4 RBS.4 3 RBS.3 2 RBS.2 1 RBS.1 0 RBS.0 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 30 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Receive Buffer Length Register (RBL): Data Sheet The RBL contains the length, in number of bytes, of the I-field storage area in internal RAM. RBL = 0 is valid (no I-field). The CPU should write RBL only when the SIU is not receiving a frame, RBE = 0. The receive buffer will not wrap around after address 191 (BFH). A buffer end is automatically generated when address 191 is reached. RBL is byte addressable. RBL Bit: 7 RBL.7 6 RBL.6 5 RBL.5 4 RBL.4 3 RBL.3 2 RBL.2 1 RBL.1 0 RBL.0 Receive Field Length Register (RFL): The RFL contains the length, in number of bytes, of the I-field of the frame received and stored in internal RAM. RFL = 0 is valid (no I-field). The CPU should access RFL only when the SIU is not receiving a frame, RBE = 0. RFL is loaded by the SIU. RFL is byte addressable. RFL Bit: 7 RFL.7 6 RFL.6 5 RFL.5 4 RFL.4 3 RFL.3 2 RFL.2 1 RFL.1 0 RFL.0 Receive Control Byte Register (RCB): The RCB contains the control field of the frame received and stored in internal RAM. RCB is only readable by the CPU and the CPU should access RCB only when the SIU is not receiving a frame, RBE = 0. RCB is loaded by the SIU. RCB is byte addressable. RCB Bit: 7 RCB.7 6 RCB.6 5 RCB.5 4 RCB.4 3 RCB.3 2 RCB.2 1 RCB.1 0 RCB.0 DMA Count Register (DMA CNT): The DMA CNT register contains the number of bytes remaining for the information field currently being used. This register is an ICE support register. DMA CNT is byte addressable. DMA CNT Bit: 7 6 DMA DMA CNT.7 CNT.6 Copyright (c) 2003 5 DMA CNT.5 4 DMA CNT.4 3 DMA CNT.3 2 DMA CNT.2 1 DMA CNT.1 0 DMA CNT.0 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 31 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER DMA Count Register (FIFO): Data Sheet The FIFO register is actually three registers that make a three byte FIFO. These are used as temporary storage between the eight bit shift register and the receive buffer when an information field is received. This register is an ICE support register. FIFO is byte addressable. FIFO Bit: 7 FIFO*.7 6 FIFO*.6 5 FIFO*.5 4 FIFO*.4 3 FIFO*.3 2 FIFO*.2 1 FIFO*.1 0 FIFO*.0 * = 1, 2 or 3 for FIFO1, FIFO2, FIFO3 respectively. SIU State Counter (SIUST): The SIUST register indicates which state the SIU state machine is currently in. This in turn indicates what task the SIU is performing or which field is expected next by the SIU. This register should not be written to. This register is an ICE support register. SIUST is byte addressable. SIUST Bit: 7 SIUST .7 6 SIUST .6 5 SIUST .5 4 SIUST .4 3 SIUST .3 2 SIUST .2 1 SIUST .1 0 SIUST .0 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 32 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Clocking Options Data Sheet The SIU may be clocked in one of two ways, with an external clock or in a self-clocked mode. In the external clocked mode a serial clock must be provided on SCLK. This clock must be synchronized to the serial data. Incoming data is sampled at the rising edge of SCLK. Outgoing data is shifted out at the falling edge of SCLK. In the self-clocked mode the SIU uses a reference clock and the serial data to reproduce the serial data clock. The reference clock can be an external source applied to SCLK, the IA8044/IA8344's internal clock or the timer 1 overflow. The reference clock must be 16x or 32x the data rate. A DPLL uses the reference clock and the serial data to adjust the sample time to the center of the serial bit. It does this by adjusting from a serial data transition in increments of 1/16 of a bit time. The maximum data rate in the externally clocked mode is 2.4Mbps in a point-to-point configuration and 1.0Mbps in a loop configuration. With a 12 MHz cpu clock the maximum data rate in the selfclocked mode with an external clock is 375Kbps. The maximum data rate in the self-clocked mode with an internal clock will depend on the frequency of the IA8044/IA8344's input clock. An IA8044/IA8344 using a 12MHz input clock can operate at a maximum data rate of 375Kbps. The Serial mode register bits 5, 6, and 7 select the clocking option for the SIU. (see SMD register description) Operational Modes The SIU operates in one of two modes, AUTO or FLEXIBLE. The mode selected determines how much intervention is required by the CPU when receiving and transmitting frames. In both modes short frames, aborted frames, and frames with CRC errors will be ignored. AUTO mode allows the SIU to recognize and respond to specific SDLC frames without the CPUs intervention. This provides for a faster turnaround time but restricts the operation of the SIU. When in AUTO mode the SIU can only act as a normal response secondary station and responses will adhere to IBM's SDLC definitions. When receiving in the AUTO mode the SIU receives the frame and examines the control byte. It will then take the appropriate action for that frame. If the frame is an information frame the SIU will load the receive buffer, interrupt the CPU and make the required response to the primary station. The SIU in AUTO mode can also respond to the following commands from the primary station. RR (Receive ready), RNR (Receive Not Ready), REJ (Reject), UP (Unnumbered Poll) also called NSP (Non-Sequenced Poll) or ORP (Optional Response Poll). In AUTO mode when the transmit buffer is full the SIU can transmit an information frame when polled for information. After transmission the SIU waits for acknowledgement from the receiving Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 33 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet station. If the response is positive the SIU interrupts the CPU. If the response is negative the SIU retransmits the frame. The SIU can send the following responses to the primary station. RR (Receive Ready), RNR (Receive Not Ready). The FLEXIBLE mode requires the CPU to control the SIU for both transmitting and receiving. This slows response time but allows full SDLC and limited HDLC compatibility as well as variations. In FLEXIBLE mode the SIU can act as a primary station. The SIU will interrupt the CPU after completion of a transmission without waiting for a positive acknowledgement from the receiving station. Basic SDLC Frame FLAG ADDRESS CONTROL INFORMATION FCS FLAG IA8X44 Frame parameters: Flag - 8 bits Address - 8 bits Control - 8 bits Information - n bytes (where n 192) FCS - 16 bits Flag - 8 bits Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 34 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Frame Format Options The various frame formats available with the IA8044/IA8344 are the standard SDLC format, the no control field format, the no control field and no address field format and the no FCS field format. The standard SDLC format consists of an opening flag, an 8-bit address field, an 8-bit control field, and n-byte information field, a 16-bit frame check sequence field and a closing flag. The FCS is generated by the CCIT-CRC polynomial (X16 +X12 + X5 + 1). The FCS is calculated on the address, control and information fields. The address and control fields may not be extended. The address is contained in STAD and the control filed is contained in either RCB or TCB. This format is supported by both AUTO and FLEXIBLE modes. The no control field format is only supported by the FLEXIBLE mode. In this format TCB and RCB are not used and the information field starts immediately after the address field. A control field may still be used in the frame but the SIU will treat it as a byte of the information field. The no control field and no address field format is only supported by the FLEXIBLE mode. In this format STAD, TCB and RCB are not used and the information field starts immediately after the opening flag. This option can only be used with the no control field option. Again a control field and address field may still be used in the frame but the SIU will treat each as a byte of the information field. The no FCS field format prevents an FCS from being generated during transmission or being checked during reception. This option may be used in conjunction with the other frame format options. This option will work with both FLEXIBLE and AUTO modes. In AUTO mode it could cause protocol violations. An FCS field may still be used in the frame but the SIU will treat it as a byte of the information field. All the possible Frame Format combinations are shown in the table below along with the bit settings that select a given format. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 35 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Frame Format Options Frame Option NFCS Standard SDLC 0 FLEXIBLE Mode Standard SDLC 0 AUTO Mode No Control Field 0 FLEXIBLE Mode No Control Field No Address Field 0 FLEXIBLE Mode No FCS Field 1 FLEXIBLE Mode No FCS Field 1 AUTO Mode No Control Field No FCS Field 1 FLEXIBLE Mode No Control Field No Address Field 1 No FCS Field FLEXIBLE Mode Fl -> Flag Ad -> Address Field Co -> Control Field Inf -> Information Field FCS -> Frame Check Sequence NB 0 0 1 1 0 0 1 AM 0 1 1 0 0 1 1 Fl Fl Fl Fl Fl Fl Fl Ad Ad Ad Inf Ad Ad Ad Frame Format Co Co Inf FCS Co Co Inf Inf Inf FCS Fl Inf Inf Fl Fl Fl FCS FCS Fl Fl Fl 1 0 Fl Inf Fl HDLC Restrictions The IA8044/IA8344 supports a subset of the HDLC protocol. The differences include the restriction by the IA8044/IA8344 of the serial data to be in 8-bit increments. In contrast HDLC allows for any number of bits in the information field. HDLC provides an unlimited address field and an extended frame number sequencing. HDLC does not support loop configuration. SIU Details The SIU is composed of two functional blocks with each having several sub blocks. The two blocks are called the bit processor (BIP) and the byte processor (BYP). Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 36 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Bit and Byte Processors BIP The BIP consists of the DPLL, NRZI encoder/decoder, serial/parallel shifter, zero insertion/deletion, shutoff logic and FCS generation/checking. The NRZI logic compares the current bit to the previous bit to determine if the bit should be inverted. The serial shifter converts the outgoing byte data to bit data and incoming bit data to byte data. The zero insert/delete circuitry inserts and deletes zeros and also detects flags(01111110), go-aheads (GA) (01111111) and aborts (1111111). The pattern 1111110 is detected as an early go-ahead that can be turned into a flag in loop configurations. The shutoff detector is a three bit counter that is used to detect a sequence of eight zeros, which is the shutoff command in loop mode transmissions. It is cleared whenever a one is detected. The FCS logic performs the generation and checking of the FCS value according to the polynomial described above. The FCS register is set to all 1's prior to each calculation. If a CRC error is generated on a receive frame the SIU will not interrupt the CPU and the error will be cleared upon receiving an opening flag. BYP The BYP contains registers and controllers used to perform the manipulations required for SDLC communications. The BYP registers may be accessed by the CPU (see SFR section above). The BYP contains the SIU state machine that controls transmission and reception of frames. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 37 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Diagnostics Data Sheet A diagnostic mode is included with the IA8044/IA8344 to allow testing of the SIU. Diagnostics use port pins P3.0 and P3.1. Writing a 0 to P3.1 enables the diagnostic mode. When P3.1 is cleared writing data to P3.0 has the effect of writing a serial data stream to the SIU. P3.0 is the serial data and any write to port 3 will clock SCLK. The transmit data may be monitored on P3.1 with any write to port 3 again clocking SCLK. In the test mode P3.0 and P3.1 pins are placed in the high impedance state. Diagnostic Signal Routing Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 38 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet AC/DC Parameters Absolute Maximum Ratings: Ambient temperature under bias....................................-40C to +85C Storage temperature..........................................................- 40C to 150C Power Supply (VDD)......................................................-0.3 to +6VDC Voltage on any pin to VSS...............................................-0.3 to (VDD +0.3) - See Note 1 Power dissipation...................................................................2W DC Characteristics Symbol VIL VIH VOL VOH RPU RPD IIL IIL1 IIH IIH1 IOZ ICC CIO Parameter Input Low Voltage Input High Voltage Output Low Voltage (IOL= 4mA) Output High Voltage (IOH= 4mA) Pull-Up Resistance (Ports 1,2,3) Pull-Down Resistance (RST) Input Low Current (Ports 1, 2, 3) Input Low Current (all other inputs) Input High Current (RST) Input High Current (all other inputs) Tri-state Leakage Current (Port 0,1,2,3) Power Supply Current (@ 12 MHz) Pin Capacitance Min 2.0 3.5 -100 -1 -1 -1 -10 Typ 50 50 Max 0.8 0.4 1 1 100 1 10 50 Unit V V V V A A A A A mA pF - 4 Notes: 1. This device does not contain EPROM or it's related programming circuitry. Therefore this limit must be adhered to especially for input pin EA that in the Intel device is used as the programming voltage pin. Exceeding the listed maximum voltage will cause damage to the device. Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 39 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet A.C. Characteristics TA = -40C to +85C, VDD = 5V 10%, VSS = 0V, Load Capacitance = 87pF External Program Memory Characteristics Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TAZPL TCY Parameter ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instr. In. ALE Low to PSENn Low PSENn Pulse Width PSENn Low to Valid Instr. In Input Instr. Hold After PSENn Input Instr. Float After PSENn PSENn to Address Valid Address to Valid Instr. In Address Float to PSENn Machine cycle 12 MHz Osc Min 171 75 74 298 83 254 215 0 76 91 373 -9 996 Max Variable Clock 1/TCLCL = 3.5 MHz TO 12 MHz Min Max 2TCLCL+4 TCLCL-8 TCLCL-9 4TCLCL-35 TCLCL 3TCLCL+4 3TCLCL-35 0 TCLCL-7 TCLCL+8 5TCLCL-43 -9 12TCLCL Unit ns ns ns ns ns ns ns ns ns ns ns ns ns External Data Memory Characteristics Symbol TRLRH TWLWH TLLAX TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RDn Pulse Width WRn Pulse Width Address Hold After ALE RDn Low to Valid Data In. Data Hold After RDn Data Float After RDn ALE Low to Valid Data In Address to Valid Data In. ALE Low to RDn or WRn Low Address to RDn or WRn Low Data Valid to WRn Transistion Data Setup Before WRn High Data Held After WRn RDn Low to Address Float RDn or WRn High to ALE High 12 MHz Osc Min 487 487 74 0 165 633 708 250 Max Variable Clock 1/TCLCL = 3.5 MHz TO 12 MHz Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min 6TCLCL-13 6TCLCL-13 TCLCL-9 0 Max 383 5TCLCL-35 2TCLCL-2 8TCLCL-34 9TCLCL-42 3TCLCL 250 325 76 563 86 83 3TCLCL 4TCLCL-8 TCLCL-7 7TCLCL-20 TCLCL+3 TCLCL 9 83 9 TCLCL Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 40 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Serial Interface Characteristics Symbol TDCY TDCL TDCH tTD tDSS tDHS Parameter Data Clock Data Clock Low Data Clock High Transmit Data Delay Data Setup Time Data Hold Time Min 420 184 184 26 58 Max Unit ns ns ns ns ns ns 125 External Clock Drive Characteristics Symbol TCLCL Parameter Oscillator Period Min 52 Max Unit ns Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 41 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Waveforms Memory Access Program Memory Read Cycle Data Sheet TCY TLHLL TLLIV TLLPL ALE TPLPH PSENn TPXAV TAVLL PORT_0 INSTR. IN A7-A0 TAZPL TLLAX TPLIV TPXIZ INSTR. IN TPXIX A7-A0 INSTR. IN TAVIV PORT_2 ADDRESS OR SFR-P2 ADDRESS A15-A8 ADDRESS A15-A8 Data Memory Read Cycle TLLDV ALE TWHLH PSENn TLLWL RDn TRLRH TAVDV TAVWL TLLAX PORT_0 A7-A0 TRLDV DATA IN TRLAZ TRHDX TRHDZ PORT_2 ADDRESS A15-A8 OR SFR-P2 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 42 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Memory Write Cycle TWHLH ALE Data Sheet PSENn TLLWL WRn TWLWH TQVWH TLLAX TAVWL TQVWX PORT_0 A7-A0 DATA OUT TWHQX PORT_2 ADDRESS A15-A8 or SFR-P2 Serial I/O Waveforms Synchronous Data Transmission TDCY TDCL SCLK TDCH TTD DATA Synchronous Data Reception TDCY TDCL SCLK TDCH TDSS DATA TDHS Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 43 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Packaging Information PLCC Package D D1 0.045*45o PIN 1 IDENTIFIER & ZONE D3 TOP VIEW E1 E E3 0.026-0.032 BOTTOM VIEW Package Dimensions for 44 Lead PLCC SEATING PLANE A Symbol A A1 D1 D2 D3 E1 E2 E3 e D E e .02 MIN. 0.013-0.021 .004 R 0.035 D2 / E2 SIDE VIEW Typical (in Inches) 0.180 0.110 0.653 0.610 0.500 0.653 0.610 0.500 0.050 0.690 0.690 www.innovasic.com Customer Support: 1-888-824-4184 Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 44 of 49 A1 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet PDIP Package TOP E1 E LEAD 1 IDENTIFIER C eB 1 LEAD COUNT DIRECTION SIDE VIEW (WIDTH) D A Package Dimensions for 40 Lead PDIP (600 mil.) Symbol Typical (in Inches) A1 L B B1 e A A1 B B1 C D E E1 e eB L 0.155 0.010 0.018 0.050 0.010 2.055 0.600 0.545 0.100 0.650 0.130 SIDE VIEW (LENGTH) Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 45 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet * Ordering Information Part Number IA8044-PDW40I-01 IA8044-PLC44I-01 IA8344-PDW40I-01 IA8344-PLC44I-01 Temperature Grade Industrial Industrial Industrial Industrial * Cross Reference to Original Part Numbers innovASIC Part Number IA8044-PLC44I q q Intel(R) Part Number N8044AH N8044AH-R0117 P8044 P8044AH P8044AH-R0117 TP8044AH TP8044AH-R0117 IA8044-PDW40I q q q q q IA8344-PLC44I q q N8344AH TN8344AH P8344 P8344AH TP8344AH IA8344-PDW40I q q q Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 46 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet * Errata Errata data listed for a particular version of the device apply only to that version. If errata data applies to more than one version it will be listed under each version affected. Errata data that applies to all versions is listed under the heading "Version ALL". InnovASIC devices are manufactured as prototypes and production units. Prototype versions are denoted as `PXX` and production versions are denoted as `XX' with XX being the version number (i.e. 03). Version ALL: ISSUE: Cannot read internal ROM with EPROM verification method. SOLUTION: Must use alternate method to read internal ROM. The IA8X44 does not contain internal EPROM and therefore does not support the EPROM read feature. ISSUE: The IA8X44 has a different pullup value than the Intel version. The Intel version can source more current than the IA8X44. SOLUTION: Adjust external circuits if necessary. Version P00: ISSUE: Incorrect version of Intel 8044 code in internal ROM. Internal ROM contains version 2.1 it should contain version 2.3. SOLUTION: Version 2.3 ROM code must be run from external memory. Future versions of device will contain version 2.3. ISSUE: The JMP @A+DPTR instruction incorrectly adds carry out of lower byte into higher byte of calculated PC value (was using carry as if the @A was a signed value, should be an absolute value). SOLUTION: Avoid use of this instruction or modify code to account for error. Future versions of device will execute this instruction correctly. ISSUE: When using edge sensitive interrupts the device may miss an interrupt. The problem occurs when enabling the interrupts or when TCON is being written to. SOLUTION: Change to level sensitive interrupts or use external registers for INT0/1. ISSUE: Reads from unused internal locations return 00h. when they should return FFh except for two locations which should return 00h. SOLUTION: Avoid reading unused locations or mask the value from unused locations. Setting IE0 or IE1 in TCON does not force an interrupt when in level sensitive mode. SOLUTION: Use edge sensitive mode for these two interrupt sources. ISSUE: Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 47 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet Port2 buffer bits set high are not actively driven when executing a MOVX A,@Ri or a MOVX @Ri,A instruction. During these instructions any bit that was driven low by the previous value on Port2 but is high in the Port2 buffer will not reach a valid high level before ALE goes low. SOLUTION: Avoid the use of these instructions or add strong pullups (approximately 10K) to Port2 externally. Race condition on transmit response in AUTO mode causes bad control byte to be transmitted.. SOLUTION: In firmware wait for RTS=1 before telling transmit to start. ISSUE: Device does not sense the end of buffer during a receive. SOLUTION: No workaround available. Receiving continuous flags (7Eh) while in loop mode will not allow a slave device to transmit. The device is only able to transmit when the line is idle. SOLUTION: Do not send continuous flags. Version 00/P01: ISSUE: The following registers change value after an external reset, STAD, TBS, TBL, TCB, RBS, RBL, RFL, and RCB. These registers should retain there pre-reset values. SOLUTION: Store register values in memory (internal or external) to be restored after reset. ISSUE: ISSUE: ISSUE: Device may miss external interrupts with narrow pulse widths when in edge sensitive mode and tight software loops that check TCON. SOLUTION: Place NOPs in loop to allow time to capture interrupt.. Intermittent drop out in slave mode, followed by normal operation. Dropouts can be caused by either noise on the reset pin or XTAL1 being unconnected when using a clock source. SOLUTION: Filter reset if necessary. Ensure that XTAL1 is tied low when using a clock source. ISSUE: When used as a slave in loop mode the device may misinterpret a byte due to an internal bit counter error. This may cause the device to think it has seen a go-ahead and can transmit when it actually should not transmit. SOLUTION: No workaround available. If the synchronous mode is used (external SCLK is provided), gating off the SCLK may cause the device to communicate erratically. Depending on when the SCLK is gated off the SIU may not have finished its present task. When the SCLK is restarted the device may not respond to communications. SOLUTION: Do not gate off the external SCLK. ISSUE: ISSUE: ISSUE: Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 48 of 49 www.innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Sheet The chip does not operate properly, showing intermittent errors. Difficulty with accessing external memory. The signals used to access external memory do not have the correct timing. SOLUTION: Adjust signal timing externally if possible. The device exhibits a 24MHz ripple on output pins. Clock/Osc switching causes noise to be induced onto power rails. SOLUTION: No workaround available. The chip fails when placed in emulators. ALE and PSEN do not tristate during reset. SOLUTION: No workaround available. ISSUE: ISSUE: ISSUE: Copyright (c) 2003 ENG210010112-00 innovASIC The End of ObsolescenceTM Page 49 of 49 www.innovasic.com Customer Support: 1-888-824-4184 |
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